JD/Expectations : -
Timing analysis, validation and debug across multiple PVT conditions using Tempus.
Familiar with Tempus DMMMC flow for STA.
STA setup, convergence, reviews, and signoff for scan.
Review of Unconstrained endpoints and check timing reports.
Proficient in STA and timing methodologies with good understanding of noise, crosstalk, and OCV effects.
Should have worked on both block level and full chip timing closure at lower nodes 22nm, 16nm, 5nm.
Additionally, closely interact with designers/synthesis/PNR team to provide the feedback to ensure smooth timing closure.
Working proficiency with tcl, python scripting .
SDF generation.
Previous experience with ADI flows for STA preferred.
We request you to use the below tracker format for submissions.
Responsibilities
JD/Expectations : -
Timing analysis, validation and debug across multiple PVT conditions using Tempus.
Familiar with Tempus DMMMC flow for STA.
STA setup, convergence, reviews, and signoff for scan.
Review of Unconstrained endpoints and check timing reports.
Proficient in STA and timing methodologies with good understanding of noise, crosstalk, and OCV effects.
Should have worked on both block level and full chip timing closure at lower nodes 22nm, 16nm, 5nm.
Additionally, closely interact with designers/synthesis/PNR team to provide the feedback to ensure smooth timing closure.
Working proficiency with tcl, python scripting .
SDF generation.
Previous experience with ADI flows for STA preferred.
We request you to use the below tracker format for submissions.
Salary : As per industry standard.
Industry :IT-Software / Software Services
Functional Area : IT Software - Application Programming , Maintenance
